Frequency multipliers have been used in a variety of applications, including RF applications. In FIG. 1, an example of a frequency multiplier 100 with positive feedback can be seen. As shown, this multiplier 100 operates to generate a differential output signal 2fLO+ and 2fLO+ that has twice the frequency of the input differential signal fLO+ and fLO−. In this example, the differential output signal 2fLO+ and 2fLO+ can function as a local oscillator signal for a modulator. The input differential signal fLO+ and fLO−, in the example of FIG. 1, is provided to the gates of transistors Q1 and Q2. Transistors Q1 and Q2 (which, as shown are NMOS transistors) are arranged to form a differential pair of transistors that are coupled between a common node and a supply rail (e.g., ground). Inductor L (which is coupled to a supply rail VDD at its center tap) is coupled to the common node of the differential pair Q1/Q2, along with the gate of transistor Q3 (which, as shown, is an NMOS transistor). The source of transistor Q3 is also coupled to the inductor L.
There are, however, some problems with this arrangement. First, the DC power consumption at RF and millimeter-wave frequencies can be high because of a finite transconductance density. Second there is a lack of biasing flexibility at the output of multiplier 100 due to the existence of a single common mode inductor tap (which, in the example of FIG. 1, is coupled to supply rail VDD). Therefore, a frequency multiplier with improved characteristics is needed.